1. Field of the Invention
This invention relates generally to voltage regulators, and more particularly to a low drop-out voltage regulator having internal compensation to optimize power supply rejection ripple.
2. Description of the Prior Art
Active compensating capacitive multiplier structures and techniques, e.g. nested Miller compensation, are well known in the art. The specific type of compensating circuit used is dependent upon the particular application. One application of improving phase margin for example, takes advantage of the Miller Effect by adding a Miller compensation capacitance in parallel with a gain stage, e.g., the output stage of a two stage amplifier circuit. Such a configuration results in the well-known and desirable phenomenon called pole splitting, which advantageously multiplies the effective capacitance of the physical capacitor employed in the circuit. See, e.g., for background on compensation of amplifier circuits using Miller-compensating capacitance, Paul R. Gray and Robert g. Meyer, Analysis and Design of Analog Integrated Circuits, Third Ed., John Wiley & sons, Inc. New York, 1993, Ch. 9, especially pp. 607-623.
Recent trends associated with high efficiency battery powered equipment are creating increased demand for power management systems using DC/DC converters feeding low drop-out (LDO) voltage regulators. Applications requiring power from such LDO voltage regulators are becoming more sensitive to noise as application bandwidth requirements are pushed ever upward. This places far greater importance on the power supply ripple rejection (PSRR) characteristics associated with LDO voltage regulators since LDO voltage regulators are used to both clean up the output noise of the DC/DC converter and to provide power supply cross talk immunity from application blocks sharing the same raw DC supply.
There is also a trend showing an increased use of ceramic capacitors as output decoupling capacitors as contrasted with the once more typical use of tantalum capacitors in such applications. The significantly low equivalent series resistance (ESR) associated with ceramic capacitors however, makes reliance on ceramic output capacitor ESR characteristics no longer feasible to stabilize an LDO amplifier control loop. Thus, a need exists in the LDO amplifier art for an internal compensation technique allowing use of a wide range of output capacitor types. Such internal compensation techniques would allow the use of much smaller output capacitors and therefore provide a means for reducing both PCB real estate requirements and external component costs.
One widely popular accepted technique associated with internal compensation is known as "Pole splitting" or "Miller Compensation" such as discussed herein above. Miller compensation, however, provides an impedance shunt across the series pass device associated with LDO voltage regulators, via the compensation capacitor and Cgs. This impedance is undesirable since it causes an early roll-off in PSRR.
The conventional two-stage PMOS low drop-out voltage regulator suffers from very poor load regulation at light, or no load, conditions. This is due to the gate of the PMOS series pass being driven from a source follower, Vdsat+Vgs, where Vt can vary from +0.2 to -0.2 V for a natural NMOS device and +0.5 to +0.9 V for a standard device. Such variations will ultimately force the first stage amplifier output devices to enter their triode region (linear mode) when the regulator is lightly loaded, resulting in a significant reduction in loop gain and hence deterioration in regulator performance.
In view of the foregoing, a need exists for an amplifier circuit architecture and technique capable of achieving higher PSRR performance from an internally compensated PMOS low drop-out voltage regulator than that presently achievable using conventional "Miller" or "Pole-splitting" techniques generally known in the art.